In the semiconductor industry, it is a well-established practice to test selected components, typically semiconductor chips packaged in a non-conductive packaging material, using known failure analysis equipment/techniques such as SEM, FIB or RIE. A major problem encountered in such activity is that the failure analysis equipment/technique imposes a severe charge on the semiconductor structure to the point where the semiconductor structure may become damaged and/or disfunctional.
Currently known methods of grounding such a packaged semiconductor device, to reduce the type of charging encountered in the type of failure analyses discussed above, typically involves touching the semiconductor device with a conductive tape or a metal probe, thus often damaging the device being analyzed, or coating the device being analyzed with carbon or gold, the presence of which could represent a major alteration of the device being tested.
In this general area, there are various solutions known and practiced with varying degrees of success. The following are a few examples of such known teachings.
U.S. Pat. No. 5,583,733 to Cronin, titled "Electrostatic Discharge Protection Device" teaches a device which automatically connects selected connector pins of a semiconductor chip package to connectors on printed circuit boards so that the connected connector pins are held at a common voltage until insertion into a receptor or until insertion of a cable into the connector which overcomes an internal resilient bias of the electrostatic discharge protection device causing the common connection to be removed. This requires reliance on a plurality of pins working in cooperation, and is therefore not a particularly simple or easy solution to the need for effective grounding of the device being tested.
U.S. Pat. No. 5,469,322 to Seo, titled "Carbon Brush for Discharging Static Electricity", discloses a carbon brush which contacts a totally enclosed semiconductor device to discharge static electricity therefrom. This arrangement requires the carbon brush to make contact with an upper or exposed portion of the semiconductor device which is to be tested.
U.S. Pat. No. 5,357,397, to Leary, titled "Electric Field Emitter Device for Electrostatic Discharge Protection of Integrated Circuits", discloses a chip design methodology to build an electrostatic discharge device into the circuitry of a semiconductor ship mounted on a wafer. This methodology therefore requires intentional addition of complexity to the basic circuitry of the semiconductor chip.
U.S. Pat. No. 5,289,336, to Gagliano, titled "Static Electricity Dispersant", discloses a technique involving the pressing of a semiconductor device into a formable or deformable material to ground the device through its leads. The actual grounding connection is made via a snap or other device to ground, and the deformed material prevents charge build-up from being transferred to other connector devices. The deformable material is electrically conductive and makes contact by being pressed into place around or onto exposed contact leads of the semiconductor device.
Finally, U.S. Pat. No. 4,945,447, to Aronson, titled "Electrostatic Grounding System for Work Surfaces", discloses an electrostatic grounding system for work surfaces, such as tabletops, with an electrostatic discharge (ESD) pad or laminate covering. The system includes a grounded conductive plug in the work surface, an area of contact between the plug and a conductive layer of the work surface being maximized by providing the plug with a head having a tapered circumference which may include ridges.
None of the above-discussed exemplary known solutions provide an adequate degree of economy, ease-of-use, simplicity, or effectiveness considered desirable for safe failure analysis of numerous samples of packaged semiconductor devices. There is, therefore, a felt need for a method which meets all of these criteria.